On Sunday, Intel held a five-hour event, where 100 attendees from startups, venture capital, and tech giants drank in semiconductor-themed cocktails and detailed explanations of how sand is processed into silicon chips. It was a celebration of how exponential upgrades from the chip industry have propelled progress in technology and society over the past 50 years — and an argument that the party’s not over. From a report: “It’s going to keep going,” said Jim Keller, a semiconductor rock star who joined Intel last year as senior vice president of silicon engineering, and a cohost of the event. “Moore’s law is relentless,” he added, referring to the 54-year-old assertion by a former Intel CEO that the number of transistors that could be fit onto a silicon chip would double on a predictable schedule.
Intel still dominates the market for server chips that power cloud computing, but its two most recent generations of chip technology arrived late. […] “The working title for this talk was ‘Moore’s law is not dead but if you think so you’re stupid,'” he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore’s law. “I’m not pedantic about Moore’s law talking just about transistors shrinking — I’m interested in the technology trends and the physics and metaphysics around that,” Keller says. “Moore’s law is a collective delusion shared by millions of people.”
Keller said Sunday that Intel can sustain that delusion, but that smaller transistors will be just one part of how. On the conventional side, he highlighted Intel’s work on extreme ultraviolet lithography, which can etch smaller features into chips, and smaller transistor designs based on nano-scale wires due to arrive in the 2020s. Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel’s 10 nanometer generation of technology. “That’s basically already working,” he said.